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1. general description the pca9698 provides 40-bit parallel input/output (i/o) port expansion for i 2 c-bus applications organized in 5 banks of 8 i/os. at 5 v supply voltage, the outputs are capable of sourcing 10 ma and sinking 25 ma with a to tal package load of 1 a to allow direct driving of 40 leds. any of the 40 i/o ports can be configured as an input or output. the pca9698 is the first gpio device in a new fast-mode plus (fm+) family. fm+ devices offer higher frequency (up to 1 mhz) and longer, more densely populated bus operation (up to 4000 pf). the device is fully configurable: output ports can be programmed to be totem-pole or open-drain and logic states can change at either the acknowledge (bank change) or the stop command (global change), each input port can be masked to prevent it from generating interrupts when its state changes, i/o data logic state can be inverted when read by the system master. an open-drain interrupt output pin (int ) allows monitoring of the input pins and is asserted each time a change occurs in one or several input ports (unless masked). the output enable pin (oe ) 3-states any i/o selected as output and can be used as an input signal to blink or dim leds (pwm with frequency > 80 hz and change duty cycle). a ?gpio all call? command allows to program mu ltiple advanced gpio s at the same time even if they have different i 2 c-bus addresses. this allows optimal code programming when more than one device needs to be programmed with the same instruction or if all outputs need to be turned on or off at the same time (for example, led test). the device id, hard coded in the pca9 698, allows the system master to read manufacturer, part type and revision information. the smbus alert feature allows the smbalert pins of multiple devices with this feature to be connected together to form a wired-and signal and to be used in conjunction with the smbus alert re sponse address. the internal power-on reset (p or) or hardware reset pin (reset ) initializes the 40 i/os as inputs. three address select pins configure one of 64 slave addresses. the pca9698 is available in 56-pin tssop and hvqfn packages and is specified over the ? 40 c to +85 c industrial temperature range. 2. features and benefits ? 1 mhz fast-mode plus i 2 c-bus serial interface ? compliant with i 2 c-bus fast-mode (400 khz) and standard-mode (100 khz) pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int rev. 3 ? 3 august 2010 product data sheet
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 2 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int ? 2.3 v to 5.5 v operation with 5.5 v tolerant i/os ? 40 configurable i/o pins that default to inputs at power-up ? outputs: ? programmable totem-pole (10 ma source, 25 ma sink) or open-drain (25 ma sink) with controlled edge rate output struct ure. default to totem-pole on power-up. ? active low output enable (oe ) input pin 3-states all outputs. polarity can be programmed to active high through the i 2 c-bus. defaults to oe on power-up. ? output state change programmable on the acknowledge or the stop command to update outputs byte-by-byte or all at th e same time respectively. defaults to acknowledge on power-up. ? inputs: ? open-drain active low interrupt (int ) output pin allows monitoring of logic level change of pins programmed as inputs ? programmable interrupt mask control for inpu t pins that do not require an interrupt when their states change ? polarity inverter register a llows inversion of the polarity of the i/o pins when read ? active low smbus alert (smbalert ) output pin allows to initiate smbus ?alert response address? sequence. own slave address sent when sequence initiated. ? active low reset (reset ) input pin resets device to power-up default state ? gpio all call address allows programming of more than one device at the same time with the same parameters ? 64 programmable slave addresses using 3 address pins ? readable device id (manufacturer, device type and revision) ? designed for live insertio n in picmg applications ? minimize line disturbance (i off and power-up 3-state) ? signal transient rejection (50 ns noise filter and robust i 2 c-bus state machine) ? low standby current ? ? 40 c to +85 c operation ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? packages offered: tssop56, and hvqfn56 3. applications ? servers ? raid systems ? industrial control ? medical equipment ? plcs ? cell phones ? gaming machines ? instrumentation and test measurement
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 3 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 4. ordering information 5. block diagram table 1. ordering information t amb = ? 40 c to +85 c type number topside mark package name description version pca9698dgg pca9698dgg tssop56 plastic thin shrink small outline package; 56 leads; body width 6.1 mm sot364-1 pca9698bs pca9698bs hvqfn56 plastic thermal enhanced very thin quad flat package; no leads; 56 terminals; body 8 8 0.85 mm sot684-1 remark: all i/os are set to inputs at power-up and reset . fig 1. block diagram of pca9698 pca9698 002aab935 low pass input filters scl sda address decoder ad0 ad1 ad2 power-on reset i 2 c-bus/smbus control reset v dd input/ output ports bank 0 lp filter int/smbalert v ss 8-bit io0_0 io0_1 io0_2 io0_3 io0_4 io0_5 io0_6 io0_7 bank 1 bank 2 bank 3 read pulse 0 write pulse 0 input/ output ports bank 4 8-bit io4_0 io4_1 io4_2 io4_3 io4_4 io4_5 io4_6 io4_7 read pulse 4 write pulse 4 oe interrupt management
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 4 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int on power-up or reset , all registers return to default values. fig 2. simplified schematic of the i/os (io0_0 to io4_7) v dd iox_y i/o configuration register dq ck q data from shift register write configuration pulse output port register dq ck polarity inversion register dq ck data from shift register write polarity pulse input port register dq ck read pulse input port register data (ix[y]) polarity inversion register data (px[y]) 002aab936 ff ff ff ff stop pulse och dq ck data from shift register write pulse ff oe oepol configuration port register data (cx[y]) output port register data (ox[y]) interrupt management int mx[y] outx
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 5 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 6. pinning information 6.1 pinning fig 3. pin configuration for tssop56 pca9698dgg sda reset scl int/smbalert io0_0 io4_7 io0_1 io4_6 io0_2 io4_5 v ss v ss io0_3 io4_4 io0_4 io4_3 io0_5 io4_2 io0_6 io4_1 v ss v dd io0_7 io4_0 io1_0 io3_7 io1_1 io3_6 io1_2 io3_5 io1_3 io3_4 io1_4 io3_3 v dd v ss io1_5 io3_2 io1_6 io3_1 io1_7 io3_0 io2_0 io2_7 v ss v ss io2_1 io2_6 io2_2 io2_5 io2_3 io2_4 ad0 oe ad1 ad2 002aab932 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 6 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 6.2 pin description fig 4. pin configuration for hvqfn56 io1_5 v dd 002aab93 4 pca9698bs transparent top view io3_0 io1_6 io1_7 io3_1 io3_2 v ss io1_4 io3_3 io1_3 io3_4 io1_2 io3_5 io1_1 io3_6 io1_0 io3_7 io0_7 io4_0 v ss v dd io0_6 io4_1 io0_5 io4_2 io0_4 io4_3 io2_0 v ss io2_1 io2_2 io2_3 ad0 ad1 ad2 oe io2_4 io2_5 io2_6 v ss io2_7 io0_3 v ss io0_2 io0_1 io0_0 scl sda reset int/smbalert io4_7 io4_6 io4_5 v ss io4_4 14 29 13 30 12 31 11 32 10 33 9 34 8 35 7 36 6 37 5 38 4 39 3 40 2 41 1 42 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 terminal 1 index area table 2. pin description symbol pin type description tssop56 hvqfn56 sda 1 50 input/output serial data line scl 2 51 input serial clock line io0_0 to io0_7 3, 4, 5, 7, 8, 9, 10, 12 52, 53, 54, 56, 1, 2, 3, 5 input/output input/output bank 0 io1_0 to io1_7 13, 14, 15, 16, 17, 19, 20, 21 6, 7, 8, 9, 10, 12, 13, 14 input/output input/output bank 1 io2_0 to io2_7 22, 24, 25, 26, 31, 32, 33, 35 15, 17, 18, 19, 24, 25, 26, 28 input/output input/output bank 2 io3_0 to io3_7 36, 37, 38, 40, 41, 42, 43, 44 29, 30, 31, 33, 34, 35, 36, 37 input/output input/output bank 3 io4_0 to io4_7 45, 47, 48, 49, 50, 52, 53, 54 38, 40, 41, 42, 43, 45, 46, 47 input/output input/output bank 4 v ss 6, 11, 23, 34, 39, 51 4, 16, 27, 32, 44, 55 [1] power supply supply ground v dd 18, 46 11, 39 power supply supply voltage ad0 27 20 input address input 0 ad1 28 21 input address input 1
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 7 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int [1] hvqfn56 package die supply ground is connected to both v ss pins and exposed center pad. v ss pins must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. 7. functional description refer to figure 1 ? block diagram of pca9698 ? . 7.1 device address following a start condit ion the bus master must send the address of the slave it is accessing and the operation it wants to pe rform (read or write). the address of the pca9698 is shown in figure 5 . slave address pins ad2, ad1 and ad0 choose 1 of 64 slave addresses. to conserve power, no internal pull-up resistors are incorporated on ad2, ad1 and ad0. address values dependi ng on ad2, ad1 and ad0 can be found in table 12 ? pca9698 address map ? . the last bit of the first byte defines the oper ation to be performed. when set to logic 1 a read is selected while a logi c 0 selects a write operation. ad2 29 22 input address input 2 oe 30 23 input active low output enable int /smbalert 55 48 output active low interrupt output/ active low smbus alert output reset 56 49 input active low reset input table 2. pin description ?continued symbol pin type description tssop56 hvqfn56 fig 5. pca9698 device address r/w 002aab93 7 a6 a5 a4 a3 a2 a1 a0 programmable slave address
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 8 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.2 alert response, gpio all call and device id addresses three other different addresses can be sent to the pca9698. ? alert response address: allows to perform an ?smbus alert? operation as defined in the smbus specification. this address is always used to perform a read operation. see section 7.11 ? smbus alert output ( smbalert ) ? for more information. ? gpio all call address: allows to program several advanced gpio devices at the same time. this address is always used to perform a write operation. see section 7.6 ? gpio all call ? for more information. ? device id address: allows to read id information from the device (manufacturer, part identification, revision). see section 7.5 ? device id - pca9698 id field ? for more information. 7.3 command register following the successful acknowle dgement of the slave address + r/w bit, the bus master will send a byte to the pca9698, wh ich will be stored in the command register. the lowest 6 bits are used as a pointer to determine which re gister will be accessed. registers are divided into 2 categories: 5-bank register category, and 1-bank register category. only a command register code with the 7 least significant bi ts equal to the 28 allowable values as defined in table 3 ? register summary ? will be acknowledged. reserved or undefined command codes will not be acknowledge d. at power-up, this register defaults to 80h, with the ai bit set to ?1?, and the lowest 7 bits set to ?0'. during a write operation, the pca9698 will ackn owledge a byte sent to the op, pi, ioc, msk, outconf, allbnk, and mode registers, but will not acknowled ge a byte sent to the ipx registers since these are read-only registers. fig 6. alert response address fig 7. gpio all call address fig 8. device id address 1 002aab93 8 0 0 0 1 1 0 0 r/w 002aab93 9 1 1 0 1 1 1 0 0 r/w r/w 002aab94 0 1 1 1 1 1 0 0 fig 9. command register 0 002aab94 1 1 0 0 0 0 0 0 d0 ai ? d5 d4 d3 d2 d1 register number auto-increment default at power-up or after reset
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 9 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.3.1 5-bank register category ? ip ? input registers ? op ? output registers ? pi ? polarity inversion registers ? ioc ? i/o configuration registers ? msk ? mask interrupt registers if the auto-increment flag is set (ai = 1), t he 3 least significant bits are automatically incremented after a read or write. this a llows the user to program and/or read the 5 register banks sequentially. if more than 5 bytes of data are written and ai = 1, previous data in the selected registers will be overwritten or reread. re served registers are skipped and not accesse d (refer to ta b l e 3 ). if the auto-increment flag is cleared (ai = 0), the 3 least significant bits are not incremented after data is read or written, only one regist er will be repeat edly read or written. 7.3.2 1-bank register category ? outconf ? output structure configuration register ? allbnk ? all bank control register ? mode ? mode selection register if more than 1 byte of data is written or read, previous data in the same register is overwritten independently of the value of ai. 7.4 register definitions table 3. register summary reg # d5 d4 d3 d2 d1 d0 name type function input port registers 00h 0 0 0 0 0 0 ip0 read only input port register bank 0 01h 0 0 0 0 0 1 ip1 read only input port register bank 1 02h 0 0 0 0 1 0 ip2 read only input port register bank 2 03h 0 0 0 0 1 1 ip3 read only input port register bank 3 04h 0 0 0 1 0 0 ip4 read only input port register bank 4 05h 0 0 0 1 0 1 - - reserved for future use 06h 0 0 0 1 1 0 - - reserved for future use 07h 0 0 0 1 1 1 - - reserved for future use
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 10 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int output port registers 08h 0 0 1 0 0 0 op0 read/write output port register bank 0 09h 0 0 1 0 0 1 op1 read/write output port register bank 1 0ah 0 0 1 0 1 0 op2 read/write output port register bank 2 0bh 0 0 1 0 1 1 op3 read/write output port register bank 3 0ch 0 0 1 1 0 0 op4 read/write output port register bank 4 0dh 0 0 1 1 0 1 - - reserved for future use 0eh 0 0 1 1 1 0 - - reserved for future use 0fh 0 0 1 1 1 1 - - reserved for future use polarity inversion registers 10h 0 1 0 0 0 0 pi0 read/write polarity inversion register bank 0 11h 0 1 0 0 0 1 pi1 read/write polarity inversion register bank 1 12h 0 1 0 0 1 0 pi2 read/write polarity inversion register bank 2 13h 0 1 0 0 1 1 pi3 read/write polarity inversion register bank 3 14h 0 1 0 1 0 0 pi4 read/write polarity inversion register bank 4 15h 0 1 0 1 0 1 - - reserved for future use 16h 0 1 0 1 1 0 - - reserved for future use 17h 0 1 0 1 1 1 - - reserved for future use i/o configuration registers 18h 0 1 1 0 0 0 ioc0 read/write i/o configuration register bank 0 19h 0 1 1 0 0 1 ioc1 read/write i/o configuration register bank 1 1ah 0 1 1 0 1 0 ioc2 read/write i/o configuration register bank 2 1bh 0 1 1 0 1 1 ioc3 read/write i/o configuration register bank 3 1ch 0 1 1 1 0 0 ioc4 read/write i/o configuration register bank 4 1dh 0 1 1 1 0 1 - - reserved for future use 1eh 0 1 1 1 1 0 - - reserved for future use 1fh 0 1 1 1 1 1 - - reserved for future use mask interrupt registers 20h 1 0 0 0 0 0 msk0 read/write mask in terrupt register bank 0 21h 1 0 0 0 0 1 msk1 read/write mask in terrupt register bank 1 22h 1 0 0 0 1 0 msk2 read/write mask in terrupt register bank 2 23h 1 0 0 0 1 1 msk3 read/write mask in terrupt register bank 3 24h 1 0 0 1 0 0 msk4 read/write mask in terrupt register bank 4 25h 1 0 0 1 0 1 - - reserved for future use 26h 1 0 0 1 1 0 - - reserved for future use 27h 1 0 0 1 1 1 - - reserved for future use miscellaneous 28h 1 0 1 0 0 0 outconf read/write output structure configuration 29h 1 0 1 0 0 1 allbnk read/write control all banks 2ah 1 0 1 0 1 0 mode read/write pca9698 mode selection table 3. register summary ?continued reg # d5 d4 d3 d2 d1 d0 name type function
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 11 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.4.1 ip0 to ip4 - input port registers these registers are read-only. they reflect the incoming logic levels of the port pins regardless of whether the pin is defined as an input or an output by the i/o configuration register. if the corresponding px[y] bit in the pi registers is set to 0, or the inverted incoming logic levels if the corr esponding px[y] bit in the pi register is set to 1. writes to these registers have no effect. the polarity inversion register can invert the logic states of the port pins. the polarity of the corresponding bit is inverted when px[y] bit in the pi register is set to 1. the polarity of the corresponding bit is not inverted when px [y] bits in the pi register is set to 0. 7.4.2 op0 to op4 - output port registers these registers reflect the out going logic levels of the pins defined as outputs by the i/o configuration register. bit values in these registers have no effect on pins defined as inputs. in turn, reads from th ese registers reflect the values that are in the flip-flops controlling the outp ut selection, not the actual pin values. ox[y] = 0: iox_y = 0 if iox_y defined as output (cx[y] in ioc register = 0). ox[y] = 1: iox_y = 1 if iox_y defined as output (cx[y] in ioc register = 0). where ?x? refers to the bank number (0 to 4); ?y? refers to the bit number (0 to 7). table 4. ip0 to ip4 - input port registers (address 00h to 04h) bit description legend: * default value ?x? determined by the externally applied logic level. address register bit symbol access value description 00h ip0 7 to 0 i0[7:0] r xxxx xxxx* i nput port register bank 0 01h ip1 7 to 0 i1[7:0] r xxxx xxxx* i nput port register bank 1 02h ip2 7 to 0 i2[7:0] r xxxx xxxx* i nput port register bank 2 03h ip3 7 to 0 i3[7:0] r xxxx xxxx* i nput port register bank 3 04h ip4 7 to 0 i4[7:0] r xxxx xxxx* i nput port register bank 4 table 5. op0 to op4 - output port register s (address 08h to 0ch) bit description legend: * default value. address register bit symbol access value description 08h op0 7 to 0 o0[7:0] r/w 0000 0000* output port register bank 0 09h op1 7 to 0 o1[7:0] r/w 0000 0000* output port register bank 1 0ah op2 7 to 0 o2[7:0] r/w 0000 0000* output port register bank 2 0bh op3 7 to 0 o3[7:0] r/w 0000 0000* output port register bank 3 0ch op4 7 to 0 o4[7:0] r/w 0000 0000* output port register bank 4
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 12 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.4.3 pi0 to pi4 - polarity inversion registers these registers allow inversion of the polarity of the corresponding input port register. px[y] = 0: the corresponding input port register data polarity is retained. px[y] = 1: the corresponding input port register data polarity is inverted. where ?x? refers to the bank number (0 to 4); ?y? refers to the bit number (0 to 7). 7.4.4 ioc0 to ioc4 - i/o configuration registers these registers configure the direction of the i/o pins. cx[y] = 0: the corresponding port pin is an output. cx[y] = 1: the corresponding port pin is an input. where ?x? refers to the bank number (0 to 4); ?y? refers to the bit number (0 to 7). table 6. pi0 to pi4 - polarity inversion registers (address 10h to 14h) bit description legend: * default value. address register bit symbol access value description 10h pi0 7 to 0 p0[7:0] r/w 0000 0000* polarity inversion register bank 0 11h pi1 7 to 0 p1[7:0] r/w 0000 0000* polarity inversion register bank 1 12h pi2 7 to 0 p2[7:0] r/w 0000 0000* polarity inversion register bank 2 13h pi3 7 to 0 p3[7:0] r/w 0000 0000* polarity inversion register bank 3 14h pi4 7 to 0 p4[7:0] r/w 0000 0000* polarity inversion register bank 4 table 7. ioc0 to ioc4 - i/o configuration regi sters (address 18h to 1ch) bit description legend: * default value. address register bit symbol access value description 18h ioc0 7 to 0 c0[7:0] r/w 1111 1111* i/o configuration register bank 0 19h ioc1 7 to 0 c1[7:0] r/w 1111 1111* i/o configuration register bank 1 1ah ioc2 7 to 0 c2[7:0] r/w 1111 1111* i/o configuration register bank 2 1bh ioc3 7 to 0 c3[7:0] r/w 1111 1111* i/o configuration register bank 3 1ch ioc4 7 to 0 c4[7:0] r/w 1111 1111* i/o configuration register bank 4
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 13 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.4.5 msk0 to msk4 - mask interrupt registers these registers mask the interrupt due to a change in the i/o pins configured as inputs. ?x? refers to the bank number (0 to 4); ?y? refers to the bit number (0 to 7). mx[y] = 0: a level change at the i/o will generat e an interrupt if iox_y defined as input (cx[y] in ioc register = 1). mx[y] = 1: a level change in t he input port will not generate an interrupt if iox_y defined as input (cx[y] in ioc register = 1). 7.4.6 outconf - output structure configuration register this register controls the configuration of t he output ports as open-drain or totem-pole. the 4 least significant bits control the outpu t architecture for bank 0, 2 bits at a time. out001 controls the output structure for io0_0 and io0_1 out023 controls the output structure for io0_2 and io0_3 out045 controls the output structure for io0_4 and io0_5 out067 controls the output structure for io0_6 and io0_7 the 4 most significant bits control the output architectures for bank 1 to bank 4, each bit controlling one bank. out1 controls the output struct ure for bank 1 (io1_0 to io1_7) out2 controls the output struct ure for bank 2 (io2_0 to io2_7) out3 controls the output struct ure for bank 3 (io3_0 to io3_7) out4 controls the output struct ure for bank 4 (io4_0 to io4_7) outx = 0: the i/os are configured with an open-drain structure. outx = 1: the i/os are configured with a totem-pole structure. table 8. msk0 to msk4 - mask interrupt regi sters (address 20h to 24h) bit description legend: * default value. address register bit symbol access value description 20h msk0 7 to 0 m0[7:0] r/w 1111 1111* mask interrupt register bank 0 21h msk1 7 to 0 m1[7:0] r/w 1111 1111* mask interrupt register bank 1 22h msk2 7 to 0 m2[7:0] r/w 1111 1111* mask interrupt register bank 2 23h msk3 7 to 0 m3[7:0] r/w 1111 1111* mask interrupt register bank 3 24h msk4 7 to 0 m4[7:0] r/w 1111 1111* mask interrupt register bank 4 table 9. outconf - output structure configuration register (address 28h) description bit 7 6 5 4 3 2 1 0 symbol out4 out3 out2 out1 out067 out045 out023 out001 default 11111111
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 14 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.4.7 allbnk - all bank control register this register allows all the i/os configured as outputs to be programmed with the same logic value. this programming is applied to all the banks or a selection of banks. when this register is programmed, values in the output port registers are not changed and do not reflect the states of i/os configured as outputs anymore. ? b0 to b4 controls the logic level to be applied to bank 0 to bank 4, respectively. ? bx = 0: all the i/os configured as outputs in the corresponding bank x are programmed with 0s. ? bx = 1: all the i/os configured as outputs in the corresponding bank x are programmed with 1s. ? bit 5 and bit 6 are not used and can be programmed to either ?1? or ?0?. ? bsel is a filter bit that a llows programming of some ban ks only, and not the others. ? bsel = 0: when bx = 0, all the i/os configured as output in the corresponding bank x are programmed with 0s. when bx = 1, all the i/os configured as output in the corresponding bank x are programmed with their actual value from the corresponding output register. ? bsel = 1: when bx = 0, all the i/os configured as output in the corresponding bank x are programmed with their actual value from the corresponding output register. when bx = 1, all the i/os configured as output in the corresponding bank x are programmed with 1s. 7.4.7.1 examples ? if allbnk = 0xx0 0000: all i/os configured as outputs in ba nk 0 to bank 4 will be programmed with 0s, overwriting values programmed in the five output port registers. ? if allbnk = 1xx1 1111: all i/os configured as outputs in ba nk 0 to bank 4 will be programmed with 1s, overwriting values programmed in the five output port registers. ? if allbnk = 0xx0 0110: all i/os configured as outputs in banks 0 , 3, and 4 only will be programmed with 0s, overwriting values programmed in the output port registers 0, 3, and 4, while i/os configured as outputs in bank 1 and bank 2 are programmed with values in output port registers 1 and 2. table 10. allbnk - all bank control register (address 29h) description bit 7 6 5 4 3 2 1 0 symbol bsel x x b4 b3 b2 b1 b0 default 10000000
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 15 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int ? if allbnk = 1xx0 1100: all i/os configured as outp uts in bank 2 and 3 will be prog rammed with 1s, overwriting values programmed in the output port regi sters 2 and 3, while i/os configured as outputs in bank 0, 1, and 4 are programmed wi th values in output port registers 0, 1, and 4. 7.4.8 mode - pca9698 mode selection register this register allows programming of the pca9698 modes. ? oepol bit controls the polarity of oe pin. ? oepol = 0: oe pin is active low. ? oepol = 1: oe pin is active high (equivalent to oe pin). ? och bit selects the i 2 c-bus event where the state of the i/os configured as outputs change. ? och = 0: outputs change on stop command. ? och = 1: outputs change on ack. ? ioac bit controls the ability of the device to respond to a ?gpio all call? command (see section 7.6 ? gpio all call ? for more information), allowing programming of more than one device at the same time. ? ioac = 0: the device cannot resp ond to a ?gpio all call? command. ? ioac = 1: the device can respo nd to a ?gpio all call? command. remark: the ?gpio all call? command defined for the pca9698 is different from the i 2 c-bus protocol ?g eneral call? command. ? smba bit controls the capab ility of the pca9698 to resp ond to a smbalert command. ? smba = 0: pca9698 does not respond to an alert response address. ? smba = 1: pca9698 responds to an alert response address. bits 5, 6 and 7 are reserved and must be programmed with 0s. ? unused bits (bits 2, 5, 6 and 7) must be programmed with 0s for proper device operation. table 11. mode - mode selection register (address 2ah) description bit 7 6 5 4 3 2 1 0 symbol x x x smba ioac x och oepol default 00000010
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 16 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.5 device id - p ca9698 id field the device id field is a 3 byte read-only (24 bits) word giving the following information: ? 12 bits with the manufacturer name, unique per manufacturer (e.g., nxp) ? 9 bits with the part identification, assigned by manufacturer (e.g., pca9698) ? 3 bits with the die revision, assigned by manufacturer (e.g., revx) the device id is read-only, hard-wired in the device and can be accessed as follows: 1. start command 2. the master sends the reserved device id i 2 c-bus address followed by the r/w bit set to ?0? (write): ?1111 1000?. 3. the master sends the i 2 c-bus slave address of the slave device it needs to identify. the lsb is a ?don?t care? value. only one device must acknowledge this byte (the one that has the i 2 c-bus slave address). 4. the master sends a re-start command. remark: a stop command followed by a star t command will reset the slave state machine and the device id read cannot be performed. also, a stop command or a re-start command followed by an access to another slave de vice will reset the slave state machine and the device id read cannot be performed. 5. the master sends the reserved device id i 2 c-bus address followed by the r/w bit set to ?1? (read): ?1111 1001?. 6. the device id read can be done, starting with the 12 manufacturer bits (first byte + 4 msbs of the second byte), followed by the 9 part identification bits (4 lsbs of the second byte + 5 msbs of the third byte), and then the 3 die revision bits (3 lsbs of the third byte). 7. the master ends the reading sequence by nacking the last byte, thus resetting the slave device state machine and allowing the master to send the stop command. remark: the reading of the device id can be stopped anytime by sending a nack command. if the master continues to ack the bytes af ter the third byte, the pca9698 rolls back to the first byte and keeps sending the device id sequence until a nack has been detected. for the pca9698, the devi ce id is as shown in figure 10 . fig 10. pca9698 id field 0 002aab94 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 revision 0 0 0 0 0 part identification manufacturer
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 17 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.6 gpio all call a ?gpio all call? command allo ws the programming of multiple advanced gpios with different i 2 c-bus addresses at the same time. this allows to optimize code programming when the master needs to send the same inst ruction to several devices. to respond to such a command and sequence, the pca9698 needs to have its ioac bit (register 2ah, bit 3) set to 1. devices that have this bit set to 0 do not participat e in any ?gpio all call? sequence. the ?gpio all call? command can be performed only for a write operation and cannot be used in conjunction with a read operation. ? master initiates a command sequence with the start command, the ?gpio all call? command associated with a write command: start ? 1101 110 + write ? all the devices that are programmed to res pond to this comm and will acknowledge ? the master then sends the data and all the devices that are programmed to respond acknowledge the byte(s) ? the master ends the sequence by sending a stop or repeated start command. if the master initiates a ?gpio all call? sequen ce with a read command , none of the slave devices acknowledge. 7.7 output state change on ack or stop state change of the i/os programmed as outputs can be done either: ? during the ack phase every time an output po rt register is modifi ed. the output state is then updated one-by-one (at a bank level): och bit = 1 (register 2ah, bit 1) ? at a stop command allowing all the outputs to change at the exact same moment: och bit = 0 (register 2ah, bit 1). change of the outputs at the stop command allows synchronizing of all the programmed banks in a single device, and also allows synchronizing outputs of more than one pca9698. example 1: only one pca9698 is used on the i 2 c-bus and all the outputs need to change at the same time. ? och bit (mode selection register, bit 1) must be equal to ?0?. ? the master accesses the device and progra ms the output port register(s) that has (have) to be changed (up to 5 ports). ? when done, the master must generate a stop command. ? at the stop command, the pca9 698 will update the output port register(s) that has (have) been programmed and change the output states all at the same time. example 2: more than one pca9698 is used on the i 2 c-bus and all the outputs need to change at the same time. ? och bit (mode selection register, bit 1) must be equal to ?0? in all the devices. ? the master device must acce ss the devices one-by-one. ? access to each device must be separated by a re-start command.
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 18 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int ? when all the devices have been accessed, the master must generate a stop command. ? at the stop command, all the pca9698s that have been accessed will update their output port registers that have been prog rammed and change the ou tput states all at the same time. remark: after programming a pca9698, its state machine will be in a ?wait-for-stop-condition? until a stop condition is received to update the output port registers. since this state machine will be in a ?wait-state?, the part will not respond to its own address until this state machine gets out to the idle condition, which means that the device can be programmed only once and is not addressable again until a stop condition has been received. remark: the pca9698 has one level of buffers to store 5 bytes of data, and the actual output port registers will get upd ated on the stop condition. if the master sends more than 5 bytes of data (with ai = 1), the data in the buffer will get overwritten. 7.8 power-on reset when power is applied to v dd , an internal power-on reset (por) holds the pca9698 in a reset condition until v dd has reached v por . at that point, the rese t condition is released and the pca9698 registers and i 2 c-bus/smbus state machine will initialize to their default states. thereafter, v dd must be lowered below 0.2 v to reset the device. 7.9 reset input a reset can be accomplished by holding the reset pin low for a minimum of t w(rst) . the pca9698 registers and i 2 c-bus state machin e will be held in their default state until the reset input is once again high. 7.10 interrupt output (int ) the open-drain active low interrupt is activate d when one of the port pins changes state and the port pin is configured as an input and the interrupt on it is not masked. the interrupt is deactivated when the port pin input returns to its previous state or the input port register is read. it is highly recommended to program the msk register, and the ioc registers during the initialization sequence after power-up, since any change to them during normal mode operation may cause undesirable interrupt events to happen. remark: changing an i/o from an output to an input may cause a false interrupt to occur if the state of the pin does not match th e contents of the input port register. only a read of the input port register that co ntains the bit(s) image of the input(s) that generated the interrupt clears the interrupt condition. if more than one input register changed state be fore a read of the input port register is initiated, the interrupt is clea red when all the input registers containing all the inputs that changed are read. example: if io0_5, io2_3, an d io3_7 change state at the same time, the interrupt is cleared only when inreg0, inreg2, and inreg3 are read.
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 19 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.11 smbus alert output (smbalert ) the interrupt output pin (int ) can also be used as an alert line (smbalert ). the smbalert pins of multiple devices with this feature can be connected together to form a wired-and signal and can be used in conjunction with the smbus alert response address. ?smbus alert? message is 2 bytes long and allows the master to determine which device generated the alert (smbalert going low). when smba bit = 1 (register 2ah, bit 4), t he pca9698 supports the smbus alert function and its int /smbalert pin may be connected as an smbus alert signal. when a master device senses that an ?smb us alert? condition is present on the alert line (smbalert pin of the pca9698 and/or other devices going low): ? it accesses the slave device(s) through the alert response address (ara) associated with a read command: start ? 0001 100 + r/w =1. ? if the pca9698 is the device that generated the ?smbus alert? condition (and its smba bit = 1), it will acknowledge the smbus alert command and respond by transmitting its slave address on the sda line. the 8 th bit (lsb) of the slave address byte will be a zero. ? the device will acknowledge an ar a command only if the smbalert signal has been previously asserted (smbalert = low). ? if more than one device pulls its smbalert pin low, the highest priority (lowest i 2 c-bus address) device will win commu nication rights via standard i 2 c-bus arbitration during the slave address transfer. ? if the pca9698 wins the arbitration, its smbalert pin will become inactive (will go high) at the completion of the slave address transmission (9 th clock pulse, nack phase). ? if the pca9698 loses the arbitration, its smbalert pin will remain active (will stay low). ? the master ends the sequence by sending a nack and then stop command. ? if the smbalert is still low after transfer is comp lete, it means that more than one device made the request. another full transaction is then required. remark: if the master initiates an ?smbus al ert? sequence with a write command, none of the slave devices acknowledge. the smbalert is open-drain and requires a pull-up resistor to v dd . remark: if the master sends an ack after reading the i 2 c-bus slave address, the slave device keeps sending ?1?s until a nack is received.
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 20 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.12 output enable input (oe ) the configurable active low or ac tive high output enable pin a llows to enable or disable all the i/os at the same time. ? when a low level is applied to the oe pin, with oepol = 0 (register 2ah, bit 4) or a high level is applied to the oe pin, with oepol = 1 (regis ter 2ah, bit 0), all the i/os configured as outputs are enabled and the logic value programmed in their respective op registers is applied to the pins. ? when a high level is applied to the oe pin, with oepol = 0 (register 2ah, bit 0) or a low level is applied to the oe pin, with oepol = 1 (registe r 2ah, bit 0), all the i/os configured as outputs are 3-stated. for applications requiring led blinking with brightness control, this pin can be used to control the brightness by applying a high frequency pwm signal on the oe pin. leds can be blinked using the output port register s and can be dimmed using the pwm signal on the oe pin thus controlling the brightness by adjusting the duty cycle. default is oepol = 0, so if the oe pin is held high, the outputs are disabled. the oe pin needs to be pulled low or oepol changed to ?1? to enable the outputs. it is recommended to define the required polarity of the oe input by programing the value of oepol before programming the conf iguration registers (ioc register). 7.13 live insertion the pca9698 is fully sp ecified for live-insertio n applications using i off , power-up 3-states, robust state machine, and 50 ns noise filter. the i off circuitry disables the outputs, preventing damaging current backfl ow through the device when it is powered down. the power-up 3-states circuitry places the outputs in the high-impedance state during power-up and power-down, which pr events driver conflic t and bus contention. the robust state machine does not respond until it sees a valid start condition and the 50 ns noise filter will filter out any inse rtion glitches. the pca9698 will not cause corruption of active data on the bus nor will the device be damage d or cause damage to devices already on the bus when similar featured devices are being used. 7.14 standby the pca9698 goes into standby when the i 2 c-bus is idle. standby s upply current is lower than 1.0 a (typical).
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 21 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 7.15 address map table 12. pca9698 address map ad2 ad1 ad0 a6 a5 a4 a3 a2 a1 a0 address v ss scl v ss 001000020h v ss scl v dd 001000122h v ss sda v ss 001001024h v ss sda v dd 001001126h v dd scl v ss 001010028h v dd scl v dd 00101012ah v dd sda v ss 00101102ch v dd sda v dd 00101112eh v ss sclscl001100030h v ss sclsda001100132h v ss sdascl001101034h v ss sdasda001101136h v dd sclscl001110038h v dd sclsda00111013ah v dd sdascl00111103ch v dd sdasda00111113eh v ss v ss v ss 010000040h v ss v ss v dd 010000142h v ss v dd v ss 010001044h v ss v dd v dd 010001146h v dd v ss v ss 010010048h v dd v ss v dd 01001014ah v dd v dd v ss 01001104ch v dd v dd v dd 01001114eh v ss v ss scl010100050h v ss v ss sda010100152h v ss v dd scl010101054h v ss v dd sda010101156h v dd v ss scl010110058h v dd v ss sda01011015ah v dd v dd scl01011105ch v dd v dd sda01011115eh
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 22 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int scl scl v ss 1010000a0h scl scl v dd 1010001a2h scl sda v ss 1010010a4h scl sda v dd 1010011a6h sda scl v ss 1010100a8h sda scl v dd 1010101aah sda sda v ss 1010110ach sda sda v dd 1010111aeh sclsclscl1011000b0h sclsclsda1011001b2h sclsdascl1011010b4h sclsdasda1011011b6h sdasclscl1011100b8h sdasclsda1011101bah sdasdascl1011110bch sdasdasda1011111beh scl v ss v ss 1100000c0h scl v ss v dd 1100001c2h scl v dd v ss 1100010c4h scl v dd v dd 1100011c6h sda v ss v ss 1100100c8h sda v ss v dd 1100101cah sda v dd v ss 1100110cch sda v dd v dd 1100111ceh scl v ss scl1110001e0h scl v ss sda1110010e2h scl v dd scl1110011e4h scl v dd sda1110100e6h sda v ss scl1110101e8h sda v ss sda1110110eah sda v dd scl1110111ech sda v dd sda1110001eeh table 12. pca9698 address map ?continued ad2 ad1 ad0 a6 a5 a4 a3 a2 a1 a0 address
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 23 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 8. characteristics of the i 2 c-bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up re sistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 8.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see figure 11 ). 8.1.1 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is hi gh is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 12 .) fig 11. bit transfer mba60 7 data line stable; data valid change of data allowed sda scl fig 12. definition of start and stop conditions mba60 8 sda scl p stop condition s start condition
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 24 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 8.2 system configuration a device generating a message is a ?transmitter ?; a device receiving is the ?receiver?. the device that controls the message is the ?master? and the devices which are controlled by the master are the ?slaves? (see figure 13 ). 8.3 acknowledge the number of data bytes transferred betwe en the start and the stop conditions from transmitter to receiver is not limited. ea ch byte of eight bits is followed by one acknowledge bit. the acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must gen erate an acknowledge af ter the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transm itter. the device that acknowledges has to pull down the sda line during the acknowledge cl ock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse; set-up and hold times must be taken into account. a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cloc ked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition. fig 13. system configuration 002aaa966 master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver sda scl i 2 c-bus multiplexer slave fig 14. acknowledgement on the i 2 c-bus 002aaa98 7 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 25 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 8.4 bus transactions data is transmitted to the pca9698 registers using ?write byte? transfers (see figure 15 , figure 16 , figure 17 , and figure 18 ). data is read from the pca9698 registers us ing ?read byte? and ?receive byte? transfers (see figure 19 and figure 20 ).
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 26 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int oe is low (with oepol = 0) or high (with oepol = 1) to observe a change in the outputs. if more than 5 bytes are written, previous data are overwritten. fig 15. write to the 5 output ports 002aab94 4 s 1 0 0 0 1 0 0 0 a6 a5 a4 a3 a2 a1 a0 0 a slave address r/w start condition command register ai = 1 output port register bank 0 is selected a acknowledge from slave data bank 0 a acknowledge from slave data bank 1 acknowledge from slave a acknowledge from slave data bank 2 a acknowledge from slave data bank 3 a acknowledge from slave data bank 4 p stop condition a acknowledge from slave sda t v(q) write to port when och = 0 data out from port when och = 0 write to port when och = 1 data out from port when och = 1 data valid all banks data valid bank 0 data valid bank 1 data valid bank 2 data valid bank 3 data valid bank 4 t v(q)
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 27 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int oe is low (with oepol = 0) or high (with oepol = 1) to observe a change in the outputs. och = 0. when och = 1, the change in the port happens at the acknowledge phase. two, three, or four adjacent banks can be programmed by using the auto-increment feature (ai = 1) and change at the corresponding output port becomes effective at the stop command when och = 0, or at each acknowledge when och = 1. fig 16. write to a specific output port 002aab94 5 s a6 a5 a4 a3 a2 a1 a0 0 a slave address r/w start condition a acknowledge from slave data bank x p stop condition a sda t v(q) write to port data out from port data x valid ai0001d2d1d0 acknowledge from slave acknowledge from slave bank x determined by d2, d1, d0 the programing becomes effective at the acknowledge. less than 5 bytes can be programmed by using the same scheme. ?d 5 d4 d3 d2 d1 d0? refers to the first register to be programmed. if more than 5 bytes are written, previous data are overwritten (the sixth configuration register w ill roll over to the first ad dressed configuration register, the sixth polarity inversion register will roll over to the first addressed polarity inversion register , the sixth mask interrupt register will roll over to the first addressed mask interrupt register. fig 17. write to the i/o configuration, polarity inversion, or mask interrupt registers (5 banks) 002aab946 s a6 a5 a4 a3 a2 a1 a0 0 a slave address r/w start condition command register ai = 1 a acknowledge from slave data bank 0 a acknowledge from slave data bank 1 acknowledge from slave a acknowledge from slave data bank 2 a acknowledge from slave data bank 3 a acknowledge from slave data bank 4 p stop condition a sda 1 0 d5 d4 d3 d2 d1 d0 01 0000 for polarity inversion register programming bank 0 01 1000 for configuration register programming bank 0 10 0000 for mask interrupt register programming bank 0 acknowledge from slave
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 28 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int the programming becomes effective at the acknowledge. if more than 1 byte is written, previous data is overwritten. fig 18. write to the output structure configuration, all bank control, or mode selection 002aab94 7 s a6 a5 a4 a3 a2 a1 a0 0 a slave address r/w start condition command register ai = 'don't care' a acknowledge from slave data a acknowledge from slave acknowledge from slave p stop condition sda x01010d1d0 00 for output structure configuration programming 01 for all bank control register programming 10 for mode selection register programming if ai = 0, the same register is read during the whole sequence. if ai = 1, the register value is incremented after each read. when the last register bank is read, it rolls over to the first byt e of the category (see category definition in section 7.3 ? command register ? ). the int signal is released only when the last register containing an input that changed has been read. for example, when io2_4 and io4_7 change at the same time and an input port regi ster read sequence is initiated, starting with ip0, int is released after ip4 is read (and not after ip2 is read). fig 19. read from input port, output port, i/o configur ation, polarity inversion, or mask interrupt registers 002aab94 8 s a6 a5 a4 a3 a2 a1 a0 0 a slave address r/w start condition command register ai = 1 a acknowledge from slave a no acknowledge from master acknowledge from slave p stop condition sda 1 0 d5 d4 d3 d2 d1 d0 sr repeated start condition a6 a5 a4 a3 a2 a1 a0 slave address 1 a r/w acknowledge from slave data from register data a acknowledge from master first byte register determined by d4 d3 d2 d1 d0 data from register data second byte data from register data last byte d[5:0] = 00 1000 for output port register bank 0 d[5:0] = 01 0000 for polarity inversion register bank 0 d[5:0] = 01 1000 for configuration register bank 0 d[5:0] = 00 0000 for input port register bank 0 d[5:0] = 10 0000 for mask interrupt register bank 0
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 29 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int if ai = 0 or 1, the same register is read during the all sequence. fig 20. read from output structure configuration, all bank control or mode selection registers 002aab94 9 s a6 a5 a4 a3 a2 a1 a0 0 a slave address r/w start condition command register ai = 'don't care' a acknowledge from slave a no acknowledge from master acknowledge from slave p stop condition sda x01010d1d0 00 for output structure configuration register reading 01 for for all bank control register reading 10 for mode selection register reading sr repeated start condition a6 a5 a4 a3 a2 a1 a0 slave address 1 a r/w acknowledge from slave data from register data last byte at this moment master-transmitter becomes master-receiver, and slave-receiver becomes slave-transmitter. fig 21. smbus alert procedure 002aab95 0 a6 a5 a4 a3 a2 a1 a0 0 pca9698 i 2 c-bus slave address r/w a no acknowledge from master p stop condition s 0 0 0 1 1 0 0 smbus alert response address start condition 1 a r/w acknowledge from slave that generated the alert at this moment master-transmitter becomes master-receiver and slave receiver becomes slave-transmitter. smbalert smbalert signal is released (assuming that only one device generated the alert) if more than 3 bytes are read, the slave dev ice loops back to the first byte (manufac turer byte) and keeps sending data until t he master generates a ?no acknowledge?. fig 22. device id field reading 002aab951 a6 a5 a4 a3 a2 a1 a0 i 2 c-bus slave address of the device to be identified a no acknowledge from master p stop condition m 11 m 10 m9 m8 m7 m6 m5 m4 sr repeated start condition 1 a r/w s 1 1 1 1 1 0 0 device id address start condition 0 a r/w acknowledge from one or several slaves 0 a don't care acknowledge from slave to be identified 1 1 1 1 1 0 0 device id address acknowledge from slave to be identified a m3 m2 m1 m0 acknowledge from master manufacturer name = 000000000000 p8 p7 p6 p5 a acknowledge from master p4 p3 p2 p1 p0 r2 r1 r0 part identification = 000000000 revision = 000
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 30 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int only slave devices with bit ioac = 1 ans wer to the gpio al l call transaction. output port register programming becomes effective at t he stop command if och = 0, at each acknowledge if och = 1. configuration, polarity inversion, and mask interrupt registers become effective at the acknowledge. less than 5 bytes can be programmed by using the same scheme. ?d5 d4 d3 d2 d1 d0? refers to the first register to be programmed. if more than 5 bytes are written, previous data are overwritten (the sixth configuration register will roll over to the first addressed configuration register, the sixth po larity inversion register will roll over to the first addressed polarity inversion register, the sixth mask interrupt register will roll over to the first addressed mask interrupt register). fig 23. gpio all call write to the output port, i/o configuration, polarity inversion, or mask interrupt registers 002aab95 2 s 1 1 0 1 1 1 0 0 a gpio all call address r/w start condition command register ai = 1 a acknowledge from slave(s) data bank 0 a acknowledge from slave(s) data bank 1 acknowledge from slave a acknowledge from slave(s) data bank 2 a acknowledge from slave(s) data bank 3 a acknowledge from slave(s) data bank 4 p stop condition a sda 1 0 d5 d4 d3 d2 d1 d0 00 1000 for output port register programming bank 0 01 0000 for polarity inversion register programming bank 0 01 1000 for configuration register programming bank 0 acknowledge from slave 10 0000 for mask interrupt register programming bank 0 only slave devices with bit 0 ioac = 1 answer the gpio all call transaction. the programming becomes effective at the acknowledge. if more than 1 byte is written, previous data is overwritten. fig 24. gpio all call write to the output structure config uration, all bank control, or mode selection registers 002aab95 3 s 1 1 0 1 1 1 0 0 a slave address r/w start condition command register ai = 'don't care' a acknowledge from slave(s) a acknowledge from slave(s) acknowledge from slave(s) p stop condition sda x01010d1d0 00 for output structure configuration register programming 01 for all bank control register programming 10 for mode selection register programming data
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 31 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 9. application design-in information device address configured as ?0100 000x? for this example. io0_0, io0_2, io0_3, io1_0 to io3_7 are configured as outputs. io0_1, io0_4, io4_0 to io4_7 are configured as inputs. fig 25. typical application pca9698 io0_0 io0_1 scl sda v dd 002aab954 scl sda 1.6 k io0_2 io0_3 v dd v ss master controller v ss v dd 2 k subsystem 1 (e.g., temp. sensor) int subsystem 2 (e.g., counter) reset controlled switch (e.g., cbt device) a b enable reset int/smbalert oe 5 v 1.6 k reset int oe 1.1 k (optional) 2 k 1.1 k (optional) subsystem 3 (e.g., alarm system) alarm io0_4 io0_5 v dd io1_0 io3_7 24 led matrix io4_0 io4_7 alphanumeric keypad ad2 ad1 ad0
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 32 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 10. limiting values table 13. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6 v v i input voltage v ss ? 0.5 5.5 v i i input current - 20 ma v i/o voltage on an input/output pin v ss ? 0.5 5.5 v i o(iox_y) output current on pin iox_y ? 20 +50 ma i dd supply current - 500 ma i ss ground supply current - 1100 ma p tot total power dissipation - 500 mw t stg storage temperature ? 65 +150 c t amb ambient temperature operating ? 40 +85 c t j junction temperature operating - 125 c storage - 150 c
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 33 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 11. static characteristics table 14. static characteristics v dd = 2.3 v to 5.5 v; v ss =0v; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 2.3 - 5.5 v i dd supply current operat ing mode; no load; f scl = 1 mhz; ad0, ad1, ad2 = static h or l v dd =2.3v - 135 200 a v dd =3.3v - 250 400 a v dd =5.5v - 550 800 a i stb standby current no load; f scl = 0 khz; i/o = inputs; v i =v dd v dd =2.3v - 0.15 11 a v dd = 3.3 v - 0.25 12 a v dd = 5.5 v - 0.75 15.5 a v por power-on reset voltage no load; v i =v dd or v ss [1] - 1.70 2.0 v input scl; input/output sda v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i ol low-level output current v ol =0.4v 20 - - ma i l leakage current v i =v dd or v ss ? 1- +1 a c i input capacitance v i =v ss -510pf i/os v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 2 - 5.5 v i ol low-level output current v ol =0.5v; v dd =2.3v [2] 12 - - ma v ol =0.5v; v dd =3.0v [2] 17 - - ma v ol =0.5v; v dd =4.5v [2] 25 - - ma i ol(tot) total low-level output current v ol =0.5v; v dd =4.5v tssop56 package [2] --0.86a hvqfn56 package [2] --1.0a v oh high-level output voltage i oh = ? 10 ma; v dd =2.3v 1.6 - - v i oh = ? 10 ma; v dd =3.0v 2.3 - - v i oh = ? 10 ma; v dd =4.5v 4.0 - - v i lih high-level input leakage current v dd =3.6v; v i/o =v dd ? 1- +1 a i lil low-level input leakage current v dd =5.5v; v i/o =v ss ? 1- +1 a c i input capacitance - 6 7 pf c o output capacitance - 6 7 pf
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 34 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int [1] v dd must be lowered to 0.2 v in order to reset part. [2] each bit must be limited to a maximum of 25 ma and the total package limited to the package ma ximum limit due to internal bus ing limits. 11.1 performance curves interrupt int i ol low-level output current v ol =0.4v 6 - - ma c o output capacitance - 3 5 pf inputs reset and oe v il low-level input voltage ? 0.5 - +0.8 v v ih high-level input voltage 2 - 5.5 v i li input leakage current ? 1- +1 a c i input capacitance - 3 5 pf inputs ad0, ad1, ad2 v il low-level input voltage ? 0.5 - +0.3v dd v v ih high-level input voltage 0.7v dd -5.5v i li input leakage current ? 1- +1 a c i input capacitance - 3.5 5 pf table 14. static characteristics ?continued v dd = 2.3 v to 5.5 v; v ss =0v; t amb = ? 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit f scl = 400 khz; all i/os unloaded scl = v dd ; all i/os unloaded fig 26. supply current as a function of temperature fig 27. standby current as a function of temperature t amb ( c) ? 50 100 50 0 002aab955 0.4 0.8 1.2 i dd ( a) 0 3.3 v 2.3 v v dd = 5 v t amb ( c) ? 50 100 50 0 002aab956 0.4 0.8 1.2 i dd ( a) 0 3.3 v 2.3 v v dd = 5 v
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 35 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int all i/os unloaded; address pins static high or low fig 28. supply current as a function of supply voltag e fig 29. i/o sink current as a function of low-level output voltage (v dd = 2.3 v) fig 30. i/o sink current as a function of low-level output voltage (v dd = 3.0 v) fig 31. i/o sink current as a function of low-level output voltage (v dd = 4.5 v) fig 32. i/o source current as a function of high-level output voltage (v dd = 2 v) fig 33. i/o source current as a function of high-level output voltage (v dd = 3.3 v) 600 i dd ( a) 0 v dd (v) 2.0 6.0 5.0 3.0 4.0 002aab957 200 400 100 khz 400 khz f scl = 1 mhz 002aab958 v ol (v) 0 0.6 0.4 0.2 20 30 10 40 50 i sink (ma) 0 t amb = ? 40 c +25 c +85 c 002aab959 v ol (v) 0 0.6 0.4 0.2 20 30 10 40 50 i sink (ma) 0 t amb = ? 40 c +25 c +85 c 002aab960 v ol (v) 0 0.6 0.4 0.2 20 30 10 40 50 i sink (ma) 0 t amb = ? 40 c +25 c +85 c 10 20 30 i source (ma) 0 v dd ? v oh (v) 0 0.8 0.6 0.2 0.4 002aab961 t amb = ? 40 c +25 c +85 c 20 30 10 40 50 i source (ma) 0 v dd ? v oh (v) 0 0.8 0.6 0.2 0.4 002aab962 t amb = ? 40 c +25 c +85 c
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 36 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int (1) v dd =5v; i sink =10ma (2) v dd = 2.3 v; i sink =10ma (3) v dd =5v; i sink =1ma (4) v dd = 2.3 v; i sink =1ma fig 34. i/o source current as a function of high-level output voltage (v dd = 5 v) fig 35. i/o low-level output voltage as a function of temperature (1) v dd = 2.3 v; i source =10ma (2) v dd =5v; i source =10ma fig 36. high-level output voltage as a function of temperature 002aab965 v dd ? v oh (v) 0 0.6 0.4 0.2 20 30 10 40 50 i source (ma) 0 t amb = ? 40 c +25 c +85 c 0 300 200 100 400 v ol (mv) t amb ( c) ? 50 100 002aab963 (1) (2) (3) (4) 050 t amb ( c) ? 50 100 50 0 002aab964 200 400 600 v dd ? v oh (v) 0 (1) (2)
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 37 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 12. dynamic characteristics [1] t vd;ack = time for acknowledgement signal from scl low to sda (out) low. table 15. dynamic characteristics symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus fast-mode plus i 2 c-bus unit min max min max min max f scl scl clock frequency [3] 0 100 0 400 0 1000 khz t buf bus free time between a stop and start condition 4.7 - 1.3 - 0.5 - s t hd;sta hold time (repeated) start condition 4.0 - 0.6 - 0.26 - s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - 0.26 - s t su;sto set-up time for stop condition 4.0 - 0.6 - 0.26 - s t hd;dat data hold time 0 - 0 - 0 - ns t vd;ack data valid acknowledge time [1] 0.1 3.45 0.1 0.9 0.05 0.45 s t vd;dat data valid time [2] 300 - 75 - 75 450 ns t su;dat data set-up time 250 - 100 - 50 - ns t low low period of the scl clock 4.7 - 1.3 - 0.5 - s t high high period of the scl clock 4.0 - 0.6 - 0.26 - s t f fall time of both sda and scl signals [4] [6] - 300 20 + 0.1c b [5] 300 - 120 ns t r rise time of both sda and scl signals [4] [6] - 1000 20 + 0.1c b [5] 300 - 120 ns t sp pulse width of spikes that must be suppressed by the input filter [7] -50 - 50-50ns port timing t en enable time output - 80 - 80 - 80 ns t dis disable time output - 40 - 40 - 40 ns t v(q) data output valid time - 250 - 250 - 250 ns t su(d) data input set-up time 100 - 100 - 100 - ns t h(d) data input hold time 250 - 250 - 250 - ns interrupt timing t v(int_n) valid time on pin int -4 - 4-4 s t rst(int_n) reset time on pin int -4 - 4-4 s reset t w(rst) reset pulse width 4 - 4 - 4 - ns t rec(rst) reset recovery time 0 - 0 - 0 - ns t rst reset time 100 - 100 - 100 - ns
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 38 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int [2] t vd;dat = minimum time for sda data out to be valid following scl low. [3] minimum scl clock frequency is limited by t he bus time-out feature, which resets the serial bus interface if either sda or s cl is held low for a minimum of 25 ms. disable bu s time-out feature for dc operation. [4] a master device must internally provide a hold time of at least 300 ns for the sda signal (refer to the v il of the scl signal) in order to bridge the undefined region of scl?s falling edge. [5] c b = total capacitance of one bus line in pf. [6] the maximum t f for the sda and scl bus lines is specified at 300 ns . the maximum fall time for the sda output stage t f is specified at 250 ns. this allows series protection resi stors to be connected between the sda and the scl pins and the sda/scl bus lines witho ut exceeding the maximum specified t f . [7] input filters on the sda and scl inputs suppress noise spikes less than 50 ns. fig 37. definition of timing on the i 2 c-bus t sp t buf t hd;sta p p s t low t r t hd;dat t f t high t su;dat t su;sta sr t hd;sta t su;sto sda scl 002aaa986 rise and fall times refer to v il and v ih . fig 38. i 2 c-bus timing diagram scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 002aab17 5 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) 1 /f scl t r t vd;dat
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 39 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 13. test information fig 39. reset timing sda scl 002aac01 8 t rst 50 % 30 % 50 % 50 % 50 % t rec(rst) t w(rst) reset iox_y output off start t rst ack or read cycle r l = load resistance. c l = load capacitance includes jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generators. fig 40. test circuitry for switching times pulse generator v o c l 50 pf r l 500 002aac01 9 r t v i v dd dut 2v dd open v ss 500
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 40 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 14. package outline fig 41. package outline sot364-1 (tssop56) unit a 1 a 2 a 3 b p cd (1) e (2) eh e ll p qz y w v references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.2 0.1 8 0 o o 0.1 dimensions (mm are the original dimensions). notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. sot364-1 99-12-27 03-02-19 w m a a 1 a 2 d l p q detail x e z e c l x (a ) 3 0.25 128 56 29 y pin 1 index b h 1.05 0.85 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 1 8.3 7.9 0.50 0.35 0.5 0.1 0.08 0.25 0.8 0.4 p e v m a a t ssop56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm sot364 -1 a max. 1.2 0 2.5 5 mm scale mo-153
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 41 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int fig 42. package outline sot684-1 (hvqfn56) 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm d h 4.45 4.15 y 1 4.45 4.15 e 1 6.5 e 2 6.5 0.30 0.18 0.05 0.00 8.1 7.9 8.1 7.9 0.05 0.1 dimensions (mm are the original dimensions) sot684-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot684- 1 h vqfn56: plastic thermal enhanced very thin quad flat package; no leads; 5 6 terminals; body 8 x 8 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 15 28 56 43 42 29 14 1 x d e c b a e 2 01-08-08 02-10-22 terminal 1 index area terminal 1 index area 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 42 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 15. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 16. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 16.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 16.3 wave soldering key characteristics in wave soldering are:
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 43 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 16.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 43 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 6 and 17 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 43 . table 16. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 17. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 44 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 17. abbreviations msl: moisture sensitivity level fig 43. temperature profiles for large and small components 001aac84 4 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 18. abbreviations acronym description cdm charged device model dut device under test esd electrostatic discharge gpio general purpose input/output hbm human body model i 2 c-bus inter-integrated circuit bus led light emitting diode mm machine model picmg pci industrial computer manufacturers group plc programmable logic controller por power-on reset pwm pulse width modulation raid redundant array of independent discs smbus system management bus
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 45 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 18. revision history table 19. revision history document id release date data sheet status change notice supersedes pca9698 v.3 20100803 product data sheet - pca9698 v.2 modifications: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? figure 25 ? typical application ? : text below figure corrected from ?device address configured as ?0010 000x? for this example.? to ?device address configured as ?0100 000x? for this example.? ? table 14 ? static characteristics ? , sub-section ?inputs reset and oe ? is corrected by removing i oh specification. pca9698 v.2 20060719 product data sheet - pca9698_1 pca9698 v.1 (9397 750 13751) 20060224 product data sheet - -
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 46 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int 19. legal information 19.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 19.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 19.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
pca9698 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 3 ? 3 august 2010 47 of 48 nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 19.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 20. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pca9698 40-bit fm+ i 2 c-bus advanced i/o port with reset , oe and int ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 3 august 2010 document identifier: pca9698 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 21. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 functional description . . . . . . . . . . . . . . . . . . . 7 7.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 alert response, gpio all call and device id addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3 command register . . . . . . . . . . . . . . . . . . . . . . 8 7.3.1 5-bank register category . . . . . . . . . . . . . . . . . . 9 7.3.2 1-bank register category . . . . . . . . . . . . . . . . . . 9 7.4 register definitions . . . . . . . . . . . . . . . . . . . . . . 9 7.4.1 ip0 to ip4 - input port registers . . . . . . . . . . . 11 7.4.2 op0 to op4 - output port registers . . . . . . . . 11 7.4.3 pi0 to pi4 - polarity inversion registers . . . . . 12 7.4.4 ioc0 to ioc4 - i/o configuration registers. . . 12 7.4.5 msk0 to msk4 - mask interrupt registers . . . 13 7.4.6 outconf - output st ructure configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.4.7 allbnk - all bank control register. . . . . . . . . 14 7.4.7.1 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.4.8 mode - pca9698 mode selection register . . 15 7.5 device id - pca9698 id field . . . . . . . . . . . . . 16 7.6 gpio all call . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.7 output state change on ack or stop . . . . . . 17 7.8 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10 interrupt output (int ) . . . . . . . . . . . . . . . . . . . 18 7.11 smbus alert output (smbalert ) . . . . . . . . . 19 7.12 output enable input (oe ) . . . . . . . . . . . . . . . . 20 7.13 live insertion . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.14 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.15 address map . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 characteristics of the i 2 c-bus . . . . . . . . . . . . 23 8.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1.1 start and stop conditions . . . . . . . . . . . . . 23 8.2 system configuration . . . . . . . . . . . . . . . . . . . 24 8.3 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.4 bus transactions . . . . . . . . . . . . . . . . . . . . . . . 25 9 application design-in information . . . . . . . . . 31 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 32 11 static characteristics. . . . . . . . . . . . . . . . . . . . 33 11.1 performance curves. . . . . . . . . . . . . . . . . . . . 34 12 dynamic characteristics. . . . . . . . . . . . . . . . . 37 13 test information . . . . . . . . . . . . . . . . . . . . . . . 39 14 package outline. . . . . . . . . . . . . . . . . . . . . . . . 40 15 handling information . . . . . . . . . . . . . . . . . . . 42 16 soldering of smd packages . . . . . . . . . . . . . . 42 16.1 introduction to soldering. . . . . . . . . . . . . . . . . 42 16.2 wave and reflow soldering. . . . . . . . . . . . . . . 42 16.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 42 16.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 43 17 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 44 18 revision history . . . . . . . . . . . . . . . . . . . . . . . 45 19 legal information . . . . . . . . . . . . . . . . . . . . . . 46 19.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 46 19.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 19.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 46 19.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 47 20 contact information . . . . . . . . . . . . . . . . . . . . 47 21 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

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